SignalTap bugges???

I encounter a very strage prolem about signaltap. My platform is using EP3C25E144 chip, custom board. And I add 7 signals (including two clocks, one is the input to PLL and the is the output from PLL) to SignalTap file, sample depth is set to 16K. The SignalTap acquisition clock is about 5 or 10 times of the sampled signals.

When I capturing the signals, I found SignalTap sometimes mismatch the signals. For example, we name the signals to be A_clk, B_clk, C, D, E, and F. Sometime, the Signtap can put the captured A_clk data to E, and B_clk data to F. Why????

And I tried many times in QuartusII 7.2 and QuartusII 9.0, the same problems occured.

Does SignalTap have bugges when capturing multiple signals with high sample depth???

Can anyone provide any recommendations or help about this problem?