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Altera_Forum's avatar
Altera_Forum
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12 years ago

SignalTap breaks my design

I'm using the DE2-115 development kit. It contains a Cylcone IV FPGA and I am interfacing that to the on board ISP1362 USB Driver (device mode only). My design asks the ISP1362 for it's chip ID. A...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

When it does work, I mash the reset signal multiple times which resets the entire design. It continues to work. If it is broken, then the same thing happens, it continues to not work. The F6 command is a reset command. That's why in the 'working' capture INT (interrupt) goes low.

I've contacted NXP, the current owner/maker of the chip and hopefully they can give me some insight. The goal is (was) to publish the interface once it is done.

I appreciate you taking the time to help.