SignalTap breaks my design

linas, Daixiwen, thank you for your replies.

As Daixiwen pointed out, TimeQuest reports that even with 64kb buffer size my design meets all of the timing requirements, even worst case scenario.

I have deleted the db and incremental_db folders. The problem persists.

Compilation Report -> Unconstrained paths: All fields read zero.

I didn't realize that the forums constrain the uploads so badly. Use this: i.imgur.com/bSKJxGa.gif You should be able to see that the behavior at the I/O is exactly the same. F6 is reset, B5 is chip ID, 3630 is the valid value. Look at the red and blue lines which point out the valid or invalid read value. The logic analyzer is looking at the GPIO on the board which is routed (wires, not registers) from the USB I/O pins. I have probed some of the USB I/O pins to verify my design is reaching them.

I read through the entire console window after compilation, this line slightly concerns me:

Info (17049): 138 registers lost all their fanouts during netlist optimizations.

How do I find a list of those registers? I do have a 16x1k fifo that is being optimized out because I haven't started using it, yet. It is not critical to my current design.

Ignored assignments: 2, Global Signal input clock (from external source), and output of PLL clock. I have instantiated a global buffer. It doesn't seem to do anything. Time Optimization Advisor says that my base (input), virtual (I/O), or generated (PLL) clocks do not use global resources. These assignments were made in the assignment editor.

This is my SDC file. To be honest, I guessed the min/max for input/output delay. The ISP1362 USB Chip requires 22 ns max for a valid value to settle on the bus. I read the value 40 ns after asserting RD/CS, plenty of time, right?

#  Create clock constraints
create_clock -name CLOCK_50 -period 20.000 
#  Create virtual clocks  for input and output delay constraints
create_clock -name io_clk -period 20.000
#  Derive PLL Clocks
derive_pll_clocks -create_base_clocks
#  derive clock uncertainty
derive_clock_uncertainty
#  set input and output delays
set_input_delay -clock { io_clk } -max 3 
set_input_delay -clock { io_clk } -min 2 
set_output_delay -clock { io_clk } -max 3 
set_output_delay -clock { io_clk } -min 2