SignalTap breaks my design

Your answer doesn't make a lot of sense. As long as the design is properly constrained and that Timequest doesn't complain, the size of the Signaltap buffers shouldn't change the behaviour of the design itself.

JPL, are you sure that Timequest reads your constrain correctly and did constrain all the I/O's? In the Timequest report you can find the number of unconstrained ports. Check also all the warnings when it reads your constraints files and check that it did understand everything correctly.

It's difficult to see anything from your screenshots. Did you try to see what was happening on the pins of the ISP1362 with a scope or a logical analyser in both cases?

Try also and delete the db and incremental_db folders each time you recompile your project. I have several projects that actually need this to work properly. There seems to be a bug in the instantiation of some megafunctions when reusing results from the previous compile, but it is a very difficult bug to reproduce.