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Altera_Forum
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12 years ago

SignalTap breaks my design

I'm using the DE2-115 development kit. It contains a Cylcone IV FPGA and I am interfacing that to the on board ISP1362 USB Driver (device mode only). My design asks the ISP1362 for it's chip ID. A...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

The samples of SignalTap II are stored in a on-chip RAM blocks in FPGA. Your problem is that you are willing to have too much samples. RAM blocks on different locations are used and design does not work anymore. Take less samples and a slower clock for acquisition.