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Altera_Forum's avatar
Altera_Forum
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16 years ago

signaltap and mismatch between RTL simulation and signaltap

I am new to signaltap and also had some questions. I have this code ... always @(posedge signal_delayed_2 or negedge reset_n) begin if (!reset_n) start_signal1 <= 8'h00; ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

There isn't enough information I am afraid.

All you have is start_signal1 chasing counter(one register in between). Ofcourse start_signal1 should follow counter by one clk edge. But is your signaltap sampling clk correct and is there anything else driving start_signal1. You better post all your code to see what you have done!