signaltap and mismatch between RTL simulation and signaltap

I am getting signal_nodelay (asyncronous to my clock) and then I pass it through 2 flip-flops for synchronizing it to my clock.

The counter is running synchronized to the clock.

so if the posedge of signal_delayed_2 occurs when counter = xAA2 signaltap would sometimes report that start_signal1= xAA0 or xAA4 or xAA2 at various samples.

also wouldn't I delay the assignment of counter to start_signal1 by 1 timeunit after the posedge of signal_delayed_2