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Altera_Forum's avatar
Altera_Forum
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16 years ago

signaltap and mismatch between RTL simulation and signaltap

I am new to signaltap and also had some questions. I have this code ... always @(posedge signal_delayed_2 or negedge reset_n) begin if (!reset_n) start_signal1 <= 8'h00; ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Your problem is not clear. But I observe:

your clk named signal_delayed_2 sounds gated...beware of gated clk problems.

your# 1 is ignored in synthesis

if your start_signal1 is delayed by 2 clks then it will follow counter by two clks leading to +-2 difference depending on how you are kicking the counter...