SignalTap - II question

If grabbing a register that doesn't get synthesized out, then there should be no need for these attributes. Most SignalTap users never apply these attributes.

I recommend tapping registers with SignalTap, but if you want to grab a wire and do it post-fit, then the keep is often necessary.

The only reason to do post-fit is that you don't have to do a full compile again. If you don't mind doing that, then pre-synthesis is much easier. (This is because synthesis can keep any wire you tap or anything like that. Post-fit is the design synthesized down to LUTs and regs, and if a name has been lost there is no way to get it back).

Pre-syntheis and post-fit are separate from modelsim. If you can find the issue in modelsim, that is by far the better way to go. SignalTap is for hunting down bugs that occur in hardware but not in your simulation. That may be because your hardware has cases/complications that are not in your testbench. It may be because you have invalid timing constraints that don't show up in simulation(like a bus passing between two unrelated clock domains). There are all sorts of reasons hardware doesn't work and the user can't find it in their simulations. That is when to use SignalTap. The reason to choose post-fit is that:

a) You don't have to run a full compile, which can be a pain when it's an 8 hour compile, or:

b) It's a problem that jumps around, e.g. on one place-and-route you see it, but then you add SignalTap and recompile from scratch(so everything gets a new fit) and the problem goes away. Post-fit allows you to lock down the locations of that previous fit.