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Altera_Forum's avatar
Altera_Forum
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13 years ago

Signals removed during synthesis - lost fanout

Hi, I am hoping someone can help me with this, I have a design written in VHDL which I have operational under RTL simulation. When I try to complie the design for Gate-level simulation a number...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

but the fact that you can change it from an external source should mean it doesnt get removed. So I still suggest that part of the design is wrong.