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Altera_Forum's avatar
Altera_Forum
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13 years ago

Signals removed during synthesis - lost fanout

Hi, I am hoping someone can help me with this, I have a design written in VHDL which I have operational under RTL simulation. When I try to complie the design for Gate-level simulation a number...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

If you leave logic in that ultimately does nothing, why do you want to leave it in? IMHO, the only reason to include noprune is for signals you want to debug with signaltap that is only there for monitoring in signal tap. Otherwise its just wasted logic that does nothing.