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Altera_Forum's avatar
Altera_Forum
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13 years ago

Signals removed during synthesis - lost fanout

Hi, I am hoping someone can help me with this, I have a design written in VHDL which I have operational under RTL simulation. When I try to complie the design for Gate-level simulation a number...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Thanks for the reply,

No Prune seems to have solved my problem for the moment :). I was setting up an LUT which now seems to be OK under both RTL and Gate level simulation. Gate level simulation takes an eternity though!

RE: design errors are you referring to the way in which the design is implemented? Wouldn't I get an error message or at least a warning or info message if that were the case?

David