Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Signals removed during synthesis - lost fanout

Hi, I am hoping someone can help me with this, I have a design written in VHDL which I have operational under RTL simulation. When I try to complie the design for Gate-level simulation a number...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

All signals that have no direct or indirect effect on the design output will be removed. The "useful" signals you refer to would be expected to have an indirect effect on the design output, I assume.

You should consider however the case, that some signals that are thought to be essential for the design are actually ignored due to design errors.

Noprune can also keep registers that are meaningless for the design output.