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Altera_Forum's avatar
Altera_Forum
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13 years ago

Signals removed during synthesis - lost fanout

Hi, I am hoping someone can help me with this, I have a design written in VHDL which I have operational under RTL simulation. When I try to complie the design for Gate-level simulation a number...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Would I be right in thinking I need to make use of the noprune VHDL synthesis attribute to solve this problem?

Thanks