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Altera_Forum
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18 years ago

signal transfer in different clock domains

CLKA & CLKB are unrelated. Signal generated from CLKA can be used as syn-clear or syn-reset signal in CLKB domain directly, right? And if we usd signal generated from CLKA as asyn-clear or asyn-...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Hi, I'm newer in HDL design.

For me, the more important is 'why do in that way' but not 'how to do'.

Looking forward for more detailed info.

Thanks :)