Signal Tap Logic Analyzer II Trigger Condition

Hi i am working with DE1-SoC Cyclone V SoC FPGA Board and i am using quartus Prime Lite Edition. I am trying to use Signal Tap Logic Analyzer II but somehow i am not able to configure it correctly my trigger condition get triggered successfully but the data log in the logic analyzer is just the last value rather than all the previous values occur before trigger condition. What can be possible thing i am missing. Any guide on this topic will be very helpful.

thanks in advance