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Altera_Forum
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8 years ago

Signal Tap II Terasic Blaster Compatibility

System: Quartus Prime V16.1 HW: Cyclone V product board with JTAG header. FPGA Design: A Qsys system with JTAG to Avalon Master bridge, OnChip memory, Clock Source, and System ID Peripheral ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Issue solved. External reset source is asserted(inverted logic)!