Signal Tap II Logic Analyzer function

Hy everyone..

I have a system of SOPC here (attached* pic1).

I access my SOPC using NIOS II IDE,by using a simple read/write function through it.(*attached pic2)

my objective here is to monitor the input and output pin to and from SDRAM(which is sdram.v file for SOPC builder), that's why I'm using the Signal Tap II Logic Analyzer.

I am following below instruction to create and use this function:

http://www.altera.com/literature/an/an323.pdf

(I'll call Signal Tap II as STII later)

The step stuck on the "create a new signaltap ii file and add signals to monitor" step (2f). This is the step to find the clock of my system.

Since i can't find any nodes when my filter setting was set to "all" , so I changed the filter to signaltapii: pre-syntesis and I got pic3(*attached pic3). From Pic1, I am assuming that my CPU clock is attached to on pll.c0, so I pick c0 as my system clock on the STII.

I add all of the input and output signal from sdram.v to the function and I got pic4.

When I run this setting together with NIOS II, I got the result but it runs so fast that I can't see the changes I want to see. I was expecting that the input address of the SDRAM will change (maybe some kind of 00_0032h)and the data will change too(maybe some kind of 0000_0032h).

I have try to trigger the falue of az_addr (which is maybe the address signal of SDRAM) to 00_0032h (attached pic4), but I cant see the expected result.

i am xpecting the result like the waveform on the modelsim or quartus waveform which can be dragged left and right to see the changing of the monitored signal.

is it possible?

Thank you in advance

Yuyex :o