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As I've mentioned before: Nios CPU also does read and write to the memory, that's why You see address changes.
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Ah .. I got it .. the memory address is keep on changing since CPU have to compile the instruction to the on-chip ram. Thank you for the guide on this :o
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Better add on-chip RAM to the SOPC and do tests there. Safe and clear how it works.
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I added on-chip memory with another specific purpose.
I am using SDRAM because my project is to improve the performance of SDRAM controller. Thank you for the advice though.
QUOTE=Socrates;142581]
For the LA You have shifted clock by -65deg for sdram chip. How can You expect to see this clock signal if every rising edge of the LA clock samples SDRAM clock at the same place? E.g.
1) SDRAM chip clk (shifted by -65deg)
2) LA sampling clock
__|--|__|--|__
___|--|__|--|__
At every rising edge of the signal (2) it samples signal (1) and the sample is always at value '1'.
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Ah~ I got what you mean.. Thank you so much, Socrates :o
Btw is there any method to see the "whole waveform action" without using trigger event, although I find it useful enough. Just wondering.
Thank you in advance
Yuyex:o
Honored Contributor
