Signal Tap II Logic Analyzer function

As I've mentioned before: Nios CPU also does read and write to the memory, that's why You see address changes. Better add on-chip RAM to the SOPC and do tests there. Safe and clear how it works.

For the LA You have shifted clock by -65deg for sdram chip. How can You expect to see this clock signal if every rising edge of the LA clock samples SDRAM clock at the same place? E.g.

1) SDRAM chip clk (shifted by -65deg)

2) LA sampling clock

__|--|__|--|__
___|--|__|--|__

At every rising edge of the signal (2) it samples signal (1) and the sample is always at value '1'.