Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

signal spy in vhdl 2008

VHDL 2008 supports a direct hierarchical reference for signals. An example hierarchy is shown below.

A <= <<signal top_ent.u_comp1.my_sig : std_logic_vector >>;

Signal 'A' can be used to spy on signal 'my_sig' in u_comp1 which is instantiated inside top_ent using the above hierarchy.

However, there is a problem. modelsim is reporting error of 'unresolved reference to top_ent.u_comp1.my_sig' if the statement above is used inside a generate statement.

SpyGenofA : if instantiateablock = true generate

.

.

.

A <= <<signal top_ent.u_comp1.my_sig : std_logic_vector >>;

.

.

.

end generate;

However, if used outside a generate statement, it works fine.

Any idea what's going on....?

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    I think the problem is the generate creates a new scope, so its looking for the top_ent inside the generate and cannot find it. I think you can use . to always reference the top of the hierarchy:

    a <= << signal .tb.dut.some_signal : std_logic >>;

    But I would suggest having a look in the modelsim help/manual