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Altera_Forum's avatar
Altera_Forum
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12 years ago

signal spy in vhdl 2008

VHDL 2008 supports a direct hierarchical reference for signals. An example hierarchy is shown below. A <= <<signal top_ent.u_comp1.my_sig : std_logic_vector >>; Signal 'A' can be used to ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

I think the problem is the generate creates a new scope, so its looking for the top_ent inside the generate and cannot find it. I think you can use . to always reference the top of the hierarchy:

a <= << signal .tb.dut.some_signal : std_logic >>;

But I would suggest having a look in the modelsim help/manual