Altera_ForumHonored Contributor12 years agoSignal related problem ----Stop the output (Urgent) module simplemotion(motion,key_0, CLK_50M,VCC); output motion; input key_0; input CLK_50M; input VCC; slowclock(CLK_50M, pulse); wire pulse; reg motion; ...Show More
Altera_ForumHonored Contributor12 years agoiT'S NOT WORKING... i just want to stop sending out the pulse
Recent DiscussionsConnection bit order between hierarchyHow to fix Error(23782): Failed to find an expected reportSolvedQuartus 22.1 and 23.1 Synthesis ErrorCould not link 'vsim_auto_compile.dll' error troubleshooting.Failed to run ip-setup-simulation: