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Maybe one thread in this forum before have discussed this topic--I just found it. We can use key words such as KEEP, NOPRUNE to set up the synthessis options, if we are using text language to do development. But the project taken over by me was developed with schematics. It seems the only thing I can do is to add pins to the nodes what I want to see.
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You don't need to, if KEEP/NOPRUNE is working, in Quartus II you can export you schematics/bdf file as verilog or vhdl under either File>Export or File>Save As Verilog (check to see which one is right, I use it sometime before), and then add the synthesis keyword to the text file. Also can point me to the thread talking on KEEP/NOPRUNE?
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