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Honored Contributor
Honored ContributorSignal not assigned in init state
Hello, I am working on a simple state machine but for some reason the output value is not assigned correctly. First it is supposed to go into state init and assign default values to my 4x8...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I dont quite know what you're talking about, as simulation always has access to all internal signal names for the waveform. If you have to access internal signals in your testbench to act on them then there is probably something wrong with the design. Btw - modelsim has signalspy to overcome internal access that you get with VHDL 2008, which has been around for a long long time --- Quote End --- Tricky, I'm probably not understanding what you are saying. You don't think it is useful for a testbench to access internal signals such as the state, count etc to see what is happening? Waveform windows are nice, but for complicated designs it is helpful to write code to verify results. I tend to agree it would be gross overkill in this case. I rarely actually modify an internal signal, but it can be useful to simulate errors.
