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Honored Contributor
Honored ContributorSignal not assigned in init state
Hello, I am working on a simple state machine but for some reason the output value is not assigned correctly. First it is supposed to go into state init and assign default values to my 4x8...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- If you are using VHDL 2008, you can access internal signal names in a testbench using the VHDL 2008 external names. Some examples here: http://stackoverflow.com/questions/17287129/vhdl-alias-syntax (http://stackoverflow.com/questions/17287129/vhdl-alias-syntax) In fact, a simulation is sort of useless if you do not do so. Being VHDL, it is ten times more verbose than necessary, but it works. Sorry for the unsought for suggestions; clearly had too much time on my hands today. --- Quote End --- I dont quite know what you're talking about, as simulation always has access to all internal signal names for the waveform. If you have to access internal signals in your testbench to act on them then there is probably something wrong with the design. Btw - modelsim has signalspy to overcome internal access that you get with VHDL 2008, which has been around for a long long time
