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PhilipJ451's avatar
PhilipJ451
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5 years ago

signal from input pin to output pin inverted

I am designing with Quartus Prime v19.1.0 for a Cyclone 10 device.

I have two clock inputs into the design and for convenience I feed these signals to output pins with test points connected (along with other signals for design analysis).

Dante_SCLK: in std_logic;
Dante_LRCK: in std_logic;

TP3: out std_logic;
TP5: out std_logic;

TP3 <= Dante_SCLK;
TP5 <= Dante_LRCK;

When examined with an oscilloscope, the signal 'Dante_SCLK' is inverted!!

This is highly misleading and results in confusion, mistakes and time wasted trying to debug why the design appears to be wrong.

Can anyone explain why this happens and what I need to do to stop it.

PhilipJ

1 Reply

  • PhilipJ451's avatar
    PhilipJ451
    Icon for New Contributor rankNew Contributor
    5 years ago

    Sorry All, ignore this!!

    Confusion with another part of the system (not FPGA) generating the signal the wrong way up, and me getting confused on the oscilloscope between 1/2 the period of the clock (~20nS) and the natural delay through the FPGA from input pin to output pin

    regards

    PhilipJ