signal_force in gate-level simulation

Nice work. SignalTap is a fantastic debug tool, but even with that, you can spend hours/days tracking down the really low-level stuff. (Or in your case, the stuff that isn't apparent without viewing the data at a higher level). But I think users have significantly better odds over timing sims.

One trick I've seen done on designs where most of the memory is used, is to put some hierarchy that is irrelevant to the problem area into a partitiont and set it to Empty. That removes that logic from the design, freeing up any RAM resources it was using, but the hierarchy boundary is preserved so nothign is ripped out upstream or downstream. Of course anything talking to that block is now unreliable, and in many cases this won't work, but I have seen a number of people be successful with those flow and never have to modify their HDL.