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Altera_Forum's avatar
Altera_Forum
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14 years ago

signal_force in gate-level simulation

Hello all, I am trying to reproduce an actual design bug in simulation. I can identify the bug in my real system by performing some statistical tricks, e.g. exciting the design with controlled...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

People,

I have gone through the gate-level netlist, and figured out the name of all the registers I need to force for simulation. Eventually, the names are very similar to the RTL, except for some synthesized out signals.

My gate-level simulation is now running without too much trouble. The only downside: it will take 25 days to complete the required 100ms!

How faster would be Modelsim PE than Modelsim-Altera Start edition? Does anyone know?

Thanks.