Should Quartus 18.1 support FF creation by this: Q <= D when rising_edge(CLK); The D and CLK are input ports on a module, and Q is a output port. The Quartus 18.1 breaks with internal error due to this construction.

This code line is standard synthesizable code.

It was specified in IEEE Std. 1076.6-2004 Clause 6.1.3.5

6.1.3.5 Edge-sensitive storage using concurrent signal assignment statements

A concurrent conditional signal assignment statement may be used to model an edge-sensitive storage element

provided that the assignment can be mapped to a process that adheres to the rules in 6.1.3.1.

Example:

COND_SIG_ASSGN: Q <= '0' when RESET = '1' else
                     '1' when SET = '1' else
                      A when ASYNC_LOAD = '1' else
                      D when CLOCK'EVENT and CLOCK = '1';

More over it was supported by previous Quartus versions as this tool was called "Altera Quartus II".

Even if it's an unsupported syntax, a tool should never crash.

In addition, this syntax is supported by all competitors (I'm listing only synthesizer tools):

• Xilinx ISE
• Xilinx Vivado
• Lattice LSE
• Synopsys Simplify PRO

Kind regards

Patrick Lehmann

Vice-Chair of the IEEE P1076 Working Group