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Firstly I suggest to use fixed point arithmetic instead of floating point which reduces resource usage and number of pipeline stages.
Secondly I don't see the advantage of the high 150 MHz clock frequency with 100 kHz sample rate. A moderate clock like 40 or 50 MHz that allows to perform an elementary add or multiply operation in a single clock cycle seems more appropriate. I believe that you want a higher clock frequency for the PWM stage, but you can transfer the manipulated value to the fast clock domain before generating PWM signals.
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Thanks for the answer!!
Good comments but my focus is somewhere else:
First how do i plan the delay and synchronization of complicated designs with multiple feedbacks (do I do it by experience or is there any theory or methodology behind it?).
Second, since you mention it, fixed point will create another iteration loop in my design as I have to also think about word sizes and precision. But anyway is also some theory and methodology behind the fixed point design?
And third, can I escape all this (including delay design) by using DSP Builder?
Thanks in advance
Honored Contributor
