Shift delay block (data valid) in simple PI controller using ALTERA FP libraries

Firstly I suggest to use fixed point arithmetic instead of floating point which reduces resource usage and number of pipeline stages.

Secondly I don't see the advantage of the high 150 MHz clock frequency with 100 kHz sample rate. A moderate clock like 40 or 50 MHz that allows to perform an elementary add or multiply operation in a single clock cycle seems more appropriate. I believe that you want a higher clock frequency for the PWM stage, but you can transfer the manipulated value to the fast clock domain before generating PWM signals.