Setup time constraints

Thanks for the explanation Batfink.

So would it be true to say (assuming the clk and data arrive at the pin at the same point in time) that the Tsu would be the difference in the routing and propagation delays between the the clock and data plus the actual setup up time that would be required?

So by placing a Tsu constraint it is actually affecting the routing delays to the register pins? (Its probably what does always but I never realised)

I'm going to delete these constaints but just one more thing I'm curious about:

As quartus does not know when the clock or data wil arrive at the input pins. Does quartus try and match the propagation and rounting delays of the clock and data inputs (or any input pin for that matter), or could one input pin have a completely different delay from the nexy?

So is it the reponsibility of the designer to ensure that a constraint is put in place if the data and clock are presented to the input pins too close together and the setup time is not met?

Many thanks again for the help.