Setup time constraints

Hi Ardni

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I understood that Tsu meant that the signal had to be present at the input pin a specified amount of time before a clk edge...

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Basically you are right here except that the setup time is for the register - i.e. the time that the input to the register has to be stable for before a clock edge. If you assume that the signal and clk edge arrive at FPGA pins together then the setup time is the routing delay inside the chip and propagation delay of any combinatorial logic in front of the register. If you make any change to the chip then it will affect the timing to some degree or other - for some designs any change or recompilation will be a real pain if you are really tight on resources and performance; for other designs you could pretty much forget about it.

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I am thinking that it is not nessesery to have these constraints and that I can safely remove them. As the interface is asynchrous and each signal that is read in from the outside is passed through a couple of flip flops.

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I would believe this to be correct - if the signals are not related to any clock then constraining them in this way would appear to be meaningless.

Have a look at some of the Quartus options:

compilation for speed or area

automatically add logic / registers - may help increase the speed

use fast input registers (uses the registers in the I/O cell where it can)

fast output registers (as above but output)

I'm not sure how many of these would apply to the FLEX devices (I've not used them myself) but give them a whirl and dig around and see if you can find anything else in Quartus that might help - there are many options and constraints, most of which you don't realise are there until you need them.

Good luck