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cjak's avatar
cjak
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9 months ago

Setup slack violations?

Hi, I have a design implemented in a Cyclone 10LP device, but I am struggling a bit with the Timing Analyzer. I am using Quartus Prime Lite edition 24.1. The setup-slack is violated for a number of...
Timing
cjak's avatar
cjak
Icon for Occasional Contributor rankOccasional Contributor
9 months ago

Also, the from-node and to-node are the same net internal in the FPGA, so I do not see why it should be defined as false-path... maybe I have not understood if correctly?