Forum Discussion
cjak
Occasional Contributor
Occasional ContributorSetup slack violations?
Hi, I have a design implemented in a Cyclone 10LP device, but I am struggling a bit with the Timing Analyzer. I am using Quartus Prime Lite edition 24.1. The setup-slack is violated for a number of...
ShengN_altera
Super Contributor
Super ContributorSeems like both the launch and latch clocks are asynchronous which causes the cdc with high clock skew. Please refer this link https://www.intel.com/content/www/us/en/docs/programmable/683243/22-4/constraining-cdc-paths.html for constraining cdc path.
