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Honored Contributor
Honored Contributorsetup and hold time with set_input_delay
Hello, I have some problem understanding the set_input_delay min and max constraint. Assume that you have an interface that is connected to an FPGA. This interface has a clock (Clk) and a...
Altera_ForumHonored Contributor
Honored ContributorThanks Rysc, placing derive_clock_uncertainty in the .sdc file seemed to sort it out
