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Honored Contributor
Honored Contributorsetup and hold time with set_input_delay
Hello, I have some problem understanding the set_input_delay min and max constraint. Assume that you have an interface that is connected to an FPGA. This interface has a clock (Clk) and a...
Altera_ForumHonored Contributor
Honored ContributorOk many thanks Rysc for this useful explanation! Timequest documentation is not really easy to understand...
Yet I have a question about this: 1) I do not understand why there is no relation between fpga_clk and the virtual ext_clk ? fpga_clk could not be created from ext_pll using create_generated_clock ?... (moreover there is a Quartus warning about this:" Warning: From ext_clk (Rise) to fpga_clk (Rise) (setup and hold) " 2)I don't know why "Report Fmax summary" is not available In Timequest report? It says "No paths to report", yet there is a path!