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Hello,
How can the size of a binary number be set, or extended by zeros; i.e. equivalent of Verilog's <size>'b<value>.
So in Verilog 5'b110 will give 00110b. I require the size to be adjustable in VHDL, because the code I am writing has a constant at the beginning of the program, and when the constant value is manually changed, the binary number size needs to change to compensate; otherwise the compiler says either the binary number has too little or too many bits.
Thank you
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if data1 is < 16 bits std logic and meant to be signed then extend it as follows:
data2 <= std_logic_vector(resize(signed(data1),16));
thus you extend with zeros if positive, or ones if negative.
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