set size of binary number?

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Hello,

How can the size of a binary number be set, or extended by zeros; i.e. equivalent of Verilog's <size>'b<value>.

So in Verilog 5'b110 will give 00110b. I require the size to be adjustable in VHDL, because the code I am writing has a constant at the beginning of the program, and when the constant value is manually changed, the binary number size needs to change to compensate; otherwise the compiler says either the binary number has too little or too many bits.

Thank you

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if data1 is < 16 bits std logic and meant to be signed then extend it as follows:

data2 <= std_logic_vector(resize(signed(data1),16));

thus you extend with zeros if positive, or ones if negative.

I want to extend the binary number in a case when statement as so:

PROCESS (rr)

BEGIN

CASE rr(N)((N-1) DOWNTO 0) IS

WHEN B"000" => SS0 <= 16#7E#; -- when N=3, this statement is fine

WHEN std_logic_vector(resize(unsigned((B"1")),N)) => SS0 <= 16#30#; -- when N=3, B"1" should be seen as B"001"

END CASE;

END PROCESS;

but i get the following error: can't determine type of object at or near string "1" -- found 6 possible types

this is because "1" is a string of std_logic. where it is placed, the string could either be a signed, unsigned or std_loigic_vector, so it doesnt know which one you want, so you need to qualify it. You dont actually need to type convert the B"1" to an unsined, because it can already be one. The qualifier in VHDL is '

so you need:

std_logic_vector(resize(unsigned'(B"1"),N));

Looking at your code, it might actually be a bit more readible to use a variable to cast the slice of rr to an integer before the case. Your case statement as it is currently would not work when N > 3, as you have a constant width on the zero expression. With the following code, it will work with all widths of rr, and will only synthesise to an apprirate width (to ensure this, you could constrain rr_int to the appropriate width, but it should fall out in synthesis).

PROCESS (rr)
  variable rr_int : integer;
BEGIN
  rr_int := to_integer( unsigned( rr(N)((N-1) DOWNTO 0) ));
  CASE rr_int IS
    WHEN 0 => SS0 <= 16#7E#; -- when N=3, this statement is fine
    WHEN 1 => SS0 <= 16#30#; -- when N=3, B"1" should be seen as B"001"
  END CASE;
END PROCESS;

How about:

std_logic_vector(to_unsigned(1,N))

I'm presuming IEEE libraries.

The opposite way is ususally easier, converting the switch expression to integer and using integer case constants.

P.S.: I see, Tricky suggested the same.