set_max_skew constraint

You mean two ports? The first one is tied to the option -source, saying physically where the clock is coming from, and then clock constraint is applied to the last one. (.sdc constraints like create_clock and create_generated_clock have a target they are applied to, which is implied, i.e. it's the one with no option. I wish it was more explicit too.)

This generated clock is necessary to show how clk_in get off chip(by the output port clk_out).

The routing delay to clk_in doesn't really matter, as it affects both the data and clk_out going off chip equally. You can account for different board delays between the FPGA and external latching device. Basically any board delay on the data output to external device is added to the output delay and any board delay for the clk_out to external device is subtracted.