Honored Contributor
Honored ContributorOK I understand (it needs some time to convert from classic analyzer to Timequest)
In line create_generated_clock -invert -name clk_out_ext -source [get_ports clk_in] [get_ports clk_out] you have two clocks, the incoming clk_in and outgoing clk_out. Is this a mistake? I think, if not, the master_clock option is missing. If J just write it down in this manner, the first is taken. Anyway, as far as I understand TimeQuest's calulation it always takes the incoming clk_in for calculating output_delay. As my external latching circuit sees clk_out as sample clock and this clock has a routing delay to clk_in, can I take this into account? That makes life more easy as I then have delays in both data and clock paths.
