set_max_skew constraint

Argh. Typed something up and it didn't get submitted. Here we go again...

Let's assume the clock is 20ns

create_clock -period 20.0 -name clk_in [get_ports {clk_in}]

derive_pll_clocks ;# out of habit

derive_clock_uncertainty

create_generated_clock -invert -name clk_out_ext -source [get_ports clk_in] [get_ports clk_out]

set_output_delay -clock clk_out_ext -max 4.6 [get_ports {data[*]}]

set_output_delay -clock clk_out_ext -min -4.6 [get_ports {data[*]}]

- The generated clock says a clock based on clk_in goes out clk_out. The invert option says it is inverted at the external device(the -invert does nothing to the clock inside the FPGA).

- Since the FPGA clock is not inverted but the external one is, you will have a setup relationship of 10ns and hold relationship of -10ns. That means across the interface, the data can be skewed by +/-10ns compared to the clock.

- The set_output_delays are saying that externally there is +/-4.6ns of skew being added. Since the interface allows +/-10, that leaves the FPGA with +/-5.4ns.