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Altera_Forum's avatar
Altera_Forum
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15 years ago

set_disable_timing

I have a combinational timing loop I want to get rid of in my timing path. When a generate a clock to clock report, this shows up in the report, "LOOP ; 17 ; LCCOMB_X16_Y58_N4 ; i_MPBLOCK_C...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

The set_disable_timing is only a "band-aid" until I figure out how to get rid of the loop in rtl.

Does anyone have any advice on how to analyze the loop? I see it in the timing report and can trace it in the netlist, but it is very large and I am having difficulty converting the synthesized names to rtl net names. Is there some way to match the "loop" that shows up in the timing report with the rtl?