Forum Discussion
Altera_Forum
Honored Contributor
13 years agoThe point you are making is that if you set false path then the tool wouldn't check if the delay of bits of same bus(bus skew) across domains is so bad that errors will occur without being reported. I agree that in a bad design this is a potential problem but you should pick it up in your company's regression testing. If you set min/max delay instead o false path would the tool then tell you if your delays have been achieved or not? it will certainly tell you there are violations due to asynchronous tranfer across clocks.
One way to prevent such delay is to insert registers right at the end of clk1 signals so there would be no comb. logic any further.