set_clock_groups vs. set_max_delay/set_min_delay

> The question I ask is "what does a failure look like?"

Say I want to transfer a two bit gray counter from a 125 MHz domain to a 150 MHz domain. In this case I would set the min delay to -1 ns and the max delay to 7 ns. If you instead set the max delay to 8 ns, you potentially risk that the difference in delay between the two bits is 9 ns, in which case you could miss a count value and go straight from 00 (0) to 11 (2) or even to 10 (3) then back to 11 (2).

I suppose if this is something that will never actually happen as long as there is no logic between the CDC registers (?), it would be fairly safe to start using set_clock_groups. But I'm skeptical.