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Altera_Forum's avatar
Altera_Forum
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9 years ago

set_clock_groups not being applied to pll clocks

Greetings. Brand new to this forum so apologies in advance if this is not the correct subforum. Also brand new to Altera parts/tools so apologies in advance for everything.

I am using Quartus Prime Lite Edition 16.0.0 Build 211 targeting a Cyclone IV EP4CE55F23I7

I have 2 asynchronous clocks coming into the FPGA, which I defined in my SDC file with:

create_clock -name TS_ipclk -period 31.000ns [get_ports {ipclk}]

create_clock -name TS_clk -period 50.00ns [get_ports {clk}]

set_clock_groups -asynchronous -group TS_ipclk -group TS_clk

I pass the TS_clk signal through a pll, and its output clock eventually touches some CDC structures that cross into/from TS_ipclk.

Even though I have declared the input clocks as asynchronous, they are still appearing as timing errors where the source and destination clocks are "inst5|altpll_component|auto_generated|pll1|clk[1]" and "TS_ipclk".

I tried adding:

derive_pll_clocks

to my SDC file with no luck.

Is there a way to have all timing analysis between asynchronous clocks disabled between the PLL clocks and TS_ipclk?

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    You need to explicitly add the PLL derived clocks to the groups as in: 

    set_clock_groups -asynchronous 
    -group { 
        adc_clk 
        the_adc_pll|altpll_component|auto_generated|pll1|clk 
        the_adc_pll|altpll_component|auto_generated|pll1|clk 
        the_adc_pll|altpll_component|auto_generated|pll1|clk 
    } 
    -group { 
        sys_clk 
        the_system_pll|altpll_component|auto_generated|pll1|clk 
        the_system_pll|altpll_component|auto_generated|pll1|clk 
    }

    as shown in the Altera TimeQuest User Guide.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    Vivado has a -include_generated_clocks option for the set_clock_groups constraint to handle this case. That would be a nice addition for Quartus.