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host's avatar
host
Icon for Occasional Contributor rankOccasional Contributor
30 days ago
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Serial Lite IV - Rx Simulation Issues

Hello, I'm having trouble with the RX in side when simulating the F-Tile Serial Lite IV example design.   Enviroment: - Quartus Prime Pro Edition 26.1, Windows - Questa Altera FPGA Edition-64 2...
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Simulation
  • CheepinC_altera's avatar
    CheepinC_altera
    21 days ago

    Hi,


    Thank you for the update.


    For your reference, I tested the example design simulation using the default configuration and observed a runtime of approximately one hour or more, which is consistent with what you reported.


    I also performed additional testing by removing one of the fast simulation parameters (+define+IP7581SERDES_UX_SIMSPEED) and observed a longer simulation time. Based on these results, the simulation duration you are seeing appears to be expected behavior for the provided example design.


    Sorry for the inconvenience, and thank you for your patience.

CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
21 days ago

Hi,


Thanks for your understanding. I will feedback the simulation time observation to Engineering, for better user experience. Thank you.

CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
11 days ago

Hi host,


I believe that your initial question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Altera experts. Otherwise, the community users will continue to help you on this thread. Thank you very much.