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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Serial in, Parallel out

Hi..

I have very basic question.I am sorry but i could not able to solve it so i m posting here.

In my project,

I have

clk:in bit;

SI : in std_logic;

PO : out std_logic_vector(12 downto 1);

);

here

SI = 11001011001

and i want parallel output like..

PO(1) =1 ;

PO(2) =0 ;

PO(3) =0 ;

PO(4) =1 ;

PO(5) =1 ;

PO(6) =0 ;

PO(7) =1 ;

PO(8) =0 ;

PO(9) =0 ;

PO(10) =1 ;

PO(11) =1 ;

What are the best options for this application (VHDL or schematic) ??

Thanking you.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    is SI serial? If you give me a more detail, I will give you a example.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    Hi...

    Yes SI is the serial input (SI = 11001011001) and i want parallel output like..

    PO(1) =1 ;

    PO(2) =0 ;

    PO(3) =0 ;

    PO(4) =1 ;

    PO(5) =1 ;

    PO(6) =0 ;

    PO(7) =1 ;

    PO(8) =0 ;

    PO(9) =0 ;

    PO(10) =1 ;

    PO(11) =1 ;

    This is like Serial interface..

    I hope it will be clear now.

    Thanks a lot
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    Try something like this:-

    shift_register : process(clk)

    begin

    if rising_edge(clk) then

    shift_reg(12 downto 1) <= shift_reg(11 downto 1) & SI;

    end if;

    end process shift_register;

    PO <= shift_reg;