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Altera_Forum
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14 years ago

Self-oscillation in simulating

Hi every one. I wrote a verilog fifo including the following line: always @(posedge read or posedge write or negedge rst) begin if(!rst)usedw<=8'h0; else if(read==1'b1)begin ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Your design involves a counter (usedw), it can be only synthesized as synchronous logic, using FFs. FPGA FFs only have a single clock input and thus you can only synthesize synchronous logic with a single (edge sensitive) clock and an optional asynchronous reset condition.

These are the facts, you need to consider them for your design.